Udemy – High-Level Synthesis for FPGA, Part 1-Combinational Circuits 2022-1

Udemy – High-Level Synthesis for FPGA, Part 1-Combinational Circuits 2022-1 Downloadly IRSpace

Apr 17, 2025 - 10:32 Updated: Apr 20, 2025 - 18:31

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Udemy – High-Level Synthesis for FPGA, Part 1-Combinational Circuits 2022-1

This course is an elementary introduction to high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design, which quickly becomes a must-have skill for every hardware or software engineer who is keen on utilising FPGAs for their exceptional performance and low power consumption.

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first to build the HLS design flow and skills along with the digital logic circuit concepts from scratch. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits. The other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

What you’ll learn

Designing combinational logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing combinational logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing two exciting projects with HLS

Who this course is for

Hardware engineers
Software engineers who are interested in FPGAs
Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
Digital Logic enthusiasts

Specificatoin of High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Publisher : Udemy
Teacher : Mohammad Hosseinbady
Language : English
Level : Beginner
Number of Course : 110
Duration : 7 hours and 47 minutes

Content of High-Level Synthesis for FPGA, Part 1-Combinational Circuits

High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Requirements

Understanding the basic concepts of C/C++ coding
Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado (download Vivado ML Edition, or Vivado Design Suite – HLx Editions for Windows or Linux)

Udemy – High-Level Synthesis for FPGA, Part 1-Combinational Circuits 2022-1