Udemy – Verification Series Part 2: Hands-On SystemVerilog Projects 2025-1

Verification Series Part 2: Hands-On SystemVerilog Projects The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times. SystemVerilog has become the primary choice of verification engineers to perform verification of complex RTL’s. SystemVerilog object-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimum effort.

Each complex system in FPGAs is built with the help of multiple subsystems. These subsystems can be either simple sequential components / simple combinational components / data communication protocols RTL / bus protocol RTL. Once we understand strategies to perform verification of the common subsystems, you can easily perform verification of any complex system with the same logic. Our objective for the course will be to build logic with the help of the fundamentals discussed in the first part of the course to perform verification of these common subsystems. We start our course by performing verification of data flipflops and FIFOs, then proceed to verification of common data communication protocols, viz., SPI, UART, and I2C. Finally, we will perform the verification of bus protocols, viz., ABP, AHB, AXI, and Whishbone protocol.

What you’ll learn

• Verification of Memories viz. FIFO
• Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone
• Verification of Interface Communication Protocols viz. SPI, UART, I2C
• Verification of Simple Compinational Block viz. Adder
• Verification of Simple Sequential Block viz. Data Flipflop

Who this course is for

• Anyone wish to learn Verification of the RTL with SystemVerilog

Specificatoin of Verification Series Part 2: Hands-On SystemVerilog Projects

• Publisher : Udemy
• Teacher : Kumar Khandagle
• Language : English
• Level : All Levels
• Number of Course : 88
• Duration : 7 hours and 59 minutes

Content of Verification Series Part 2: Hands-On SystemVerilog Projects

Requirements

• Fundamentals of Verilog, Digital Electronics

Pictures

Sample Clip

Installation Guide

Extract the files and watch with your favorite player

Subtitle : English

Quality: 720p

Previous Title:

SystemVerilog for Verification Part 2 : Projects

Changes:

The 2025/1 version has been reduced from 2022/9 by 65 lessons and 7 hours 55 minutes in duration.

Download Links

Download Part 1 – 1 GB

Download Part 2 – 309 MB

File size

1.3 GB