Udemy – Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT 2025-3
Udemy – Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT 2025-3 Downloadly IRSpace
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Mastering Xilinx DSP IP Cores: FIR, CIC, DDS, FFT. This course is a practical, step-by-step guide to mastering the four Xilinx DSP IP cores: FIR Compiler, CIC Compiler, DDS Compiler, and FFT, covering everything from simulation to implementation on the real hardware of the Arty Z7-20 development board. You will learn how to configure and simulate each core in Vivado 2024.2, create Verilog testbenches, and analyze the results with Python. The course explores various configurations including FIR as a bandpass filter, Hilbert transformer, interpolator and extrapolator, CIC as interpolator and extrapolator, DDS with and without phase generator, and FFT for direct and inverse transformation. Then, you will implement the designs on the Zynq-7000 SoC and manage data transfer between PS and PL via AXI DMA by developing C programs in Vitis. You will also learn how to automate the development process with TCL scripts and debug designs with System ILA. This course is suitable for FPGA beginners, digital designers, embedded engineers, and signal processing enthusiasts on the Xilinx platform, and by the end, you will have a comprehensive understanding of the design and implementation of these cores in simulation and hardware environments.
What you will learn
- How to simulate Xilinx DSP IP Cores (FIR, CIC, DDS compiler, and FFT) in Vivado with Verilog testbenches and Python analysis.
- How to integrate IP Cores into FPGA designs on a development board.
- How to develop a standalone embedded C program to communicate with DSP IP Cores.
- How to automate Vivado and Vitis workflows with TCL and Python scripts.
This course is suitable for people who:
- Beginner
- Medium
Course details: Mastering Xilinx DSP IP Cores: FIR CIC DDS FFT
- Publisher: Udemy
- Instructor: Aleksei Rostov
- Training level: Beginner to advanced
- Training duration: 2 hours and 17 minutes
- Number of lessons: 10
Course topics
Prerequisites for the Mastering Xilinx DSP IP Cores: FIR CIC DDS FFT course
- Vivado 2024.2
- Vitis 2024.2
- Python >= 3.0
- Powershell
- Any development board with Zynq 7000 SoC (Arty z7-20 as example)
Course images
Sample course video
Installation Guide
After Extract, view with your favorite player.
Subtitles: None
Quality: 720p
Download link
File(s) password: www.downloadly.ir
File size
1.8 GB
