Udemy – High-Level Synthesis for FPGA, Part 3 – Advanced 2023-1

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Apr 17, 2025 - 10:36 Updated: Aug 17, 2025 - 11:18

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Udemy – High-Level Synthesis for FPGA, Part 3 – Advanced 2023-1

This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design. It quickly becomes a must-have skill for every hardware or software engineer keen on utilising FPGAs for their exceptional performance and low power consumption. This course is the first to explain the advanced HLS design flow topics. It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications.

Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises to practice and master the proposed methods and approaches. This course is the third of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on multi-cycle design, advanced design, and optimisation techniques in HLS, the other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.

What you’ll learn

Using Multi-Cycle design flow to develop sequential circuits in HLS.
Implementing stream communication and computation in HLS
Using FIFO as the synchronisation mechanism between to connected module
Learning how to use an array variable inside an HLS code
Connecting and AND HLS IP to BRAMs in a Vivado project
Working with pointers in HLS
Working with AXI protocol in HLS
Loop pipelining optimisation in HLS
Loop unrolling optimisation in HLS
Loop flattening optimisation in HLS
Loop rewinding optimisation in HLS
Working with the HLS-Stream library in HLS
Handshaking protocol and interfaces in HLS

Who this course is for

Hardware engineers
Software engineers who are interested in FPGAs
Lecturers, researchers, and professors who want to use FPGA-based HLS in lectures, courses or research
Digital Logic enthusiasts

Specificatoin of High-Level Synthesis for FPGA, Part 3 – Advanced

Publisher : Udemy
Teacher : Mohammad Hosseinbady
Language : English
Level : Intermediate
Number of Course : 58
Duration : 7 hours and 33 minutes

Content of High-Level Synthesis for FPGA, Part 3 – Advanced

High-Level Synthesis for FPGA, Part 3 - Advanced

Requirements

Understanding the basic concepts of C/C++ coding
Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
“High-Level Synthesis for FPGA, Part 1-Combinational Circuits” Udemy course
“High-Level Synthesis for FPGA, Part 2 – Sequential Circuits” Udemy course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite – HLx Editions for Windows or Linux)

Udemy – High-Level Synthesis for FPGA, Part 3 – Advanced 2023-1